1. Field of the Invention
The present invention relates to MOSFETs having low junction capacitance and low threshold voltage and that are especially suitable for high frequency applications. More particularly, the present invention relates to annular MOSFETs for phase lock loop applications.
2. Description of the Related Art
A conventional transistor 10 fabricated using CMOS technology has a straight polysilicon gate electrode 12 and rectangular doped drain and source regions 14, 16 diffused on either side of gate 12. A typical layout is shown in FIGS. 1 and 1A. The disadvantages of such MOSFETs include junction capacitance from source or drain to field oxide regions 20 because of the relatively high dopant concentration due to field implant and leakage current from the drain to the source along the edges of the drain and source regions.
Annular transistor layouts 24, such as shown in FIGS. 2 and 2A, are also known. In this configuration, gate 12, drain 14 and source 16 are circular. In annular transistors 24, although the drain to source path does not border field oxide regions 26, the drain ring 14 does and this leads to undesirably high junction capacitance.
Threshold voltage V.sub.T, i.e., the gate voltage necessary to form a conductive channel for electrons, that is, to turn on the transistor, is an important design parameter for transistors. V.sub.T increases with increasing source to substrate bias voltage; the mechanism of this so-called "back-bias" effect is that the gate charge must first compensate for bulk charge existing on the substrate side of the channel before creating a conductive channel. Drain current I.sub.D is also affected by channel conductivity. Since higher I.sub.D is desirable because of the resulting increased device speed, it is desired to improve channel conductivity and achieve higher mobility.